Is it possible to create a simulation waveform from yosys output

Question

I found that imitation using iverilog is a less suitable method, I can simulate projects that will not synthesize and, conversely, design that will not only synthesize, but also work as intended on physical equipment, will not be synthesized using iverilog for modeling.

What I ideally want to do is draw the yosys output (blif file) and create a simulation formula (vcd) with which I can be more confident.

Answer 1

So, you want to run the postsynthetic simulation of iCl40 BLIF netlists.

Consider the following simple construction example ( test.v ):

 module test(input clk, resetn, output reg [3:0] y); always @(posedge clk) y <= resetn ? y + 1 : 0; endmodule 

And its testbench ( test_tb.v ):

 module testbench; reg clk = 1, resetn = 0; wire [3:0] y; always #5 clk = ~clk; initial begin repeat (10) @(posedge clk); resetn <= 1; repeat (20) @(posedge clk); $finish; end always @(posedge clk) begin $display("%b", y); end test uut ( .clk(clk), .resetn(resetn), `ifdef POST_SYNTHESIS . \y[0] (y[0]), . \y[1] (y[1]), . \y[2] (y[2]), . \y[3] (y[3]) `else .y(y) `endif ); endmodule 

Running a simulation before synthesis is, of course, simple:

 $ iverilog -o test_pre test.v test_tb.v $ ./test_pre 

To model after synthesis, we must first start the synthesis:

 $ yosys -p 'synth_ice40 -top test -blif test.blif' test.v 

Then we need to convert the BLIF netlist to the verilog netlist so that Icarus Verilog can read it:

 $ yosys -o test_syn.v test.blif 

Now we can build a binary simulation file from the test bench, synthesized design and iCE40 simulation models and run it:

 $ iverilog -o test_post -D POST_SYNTHESIS test_tb.v test_syn.v \ `yosys-config --datdir/ice40/cells_sim.v` $ ./test_post 

[..] will not be synthesized using iverilog for simulation.

This is most likely because Yosys is not as strict as iverilog when it comes to applying the Verilog standard. For example, in many cases, Yosys will be with the exception of Verilog files with the reg keyword not in the wire, which requires the reg keyword in accordance with the Verilog standard. For example, yosys will accept the following input, even if it is not valid Verilog code:

 module test(input a, output y); always @* y = !a; endmodule 

For Icarus Verilog you need to add the missing reg :

 module test(input a, output reg y); always @* y = !a; endmodule