Interface with 8-segment seven-segment display

Question

I have to interact with an 8-digit seven-segment display

Here's what the circuit looks like:

And here is my code:

`timescale 1ns / 1ps module TimeMUXDisplay(input clk,input [5:0] DIN, output reg [7:0] E,output reg [6:0] C,output DP); //Counter reg [19:0]Counter; initial Counter=0; always@ (posedge clk) Counter <= Counter + 1; //3-to-8 decoder always @ (Counter[19:17]) begin case(Counter[19:17]) 0: E<=8'b11111110; 1: E<=8'b11111101; 2: E<=8'b11111011; 3: E<=8'b11110111; 4: E<=8'b11101111; 5: E<=8'b11011111; 6: E<=8'b10111111; 7: E<=8'b01111111; default:E<=8'b11111111; endcase end //8-to-1 MUX reg [5:0]DOUT; always@ (DIN,Counter[19:17]) begin case(Counter[19:17]) 3'd0:DOUT<=DIN[5:0]; 3'd1:DOUT<=6'b000001; 3'd2:DOUT<=6'b000001; 3'd3:DOUT<=6'b000001; 3'd4:DOUT<=6'b000001; 3'd5:DOUT<=6'b000001; 3'd6:DOUT<=6'b000001; 3'd7:DOUT<=6'b000001; default:DOUT<=6'b000001; // indicates null endcase end // Binary-to-seven segment wire Enb; assign Enb=DOUT[5]; always @(*) begin if(Enb) case(DOUT[4:1]) 0:C<=7'b1111110; 1:C<=7'b0110000; 2:C<=7'b1101101; 3:C<=7'b1111001; 4:C<=7'b0110011; 5:C<=7'b1011011; 6:C<=7'b1011111; 7:C<=7'b1110000; 8:C<=7'b1111111; 9:C<=7'b1111011; default: C<=7'b1111111; endcase else C<=7'b1111111; end assign DP=DOUT[0]; endmodule 

But when I try to test it with Nexys 4DDR, it just doesn't work (synthesis, implementation works without problems, but 7-segment displays don't work), I don’t know why.

By the way, this is what I have in the file describing the ports, but I'm sure it is good, the problem should be in the code above:

 ## Clock signal set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk}]; ##Switches set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { DIN[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { DIN[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { DIN[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { DIN[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { DIN[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { DIN[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5] ##7 segment display set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { C[0] }]; #IO_L24N_T3_A00_D16_14 Sch=ca set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { C[1] }]; #IO_25_14 Sch=cb set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { C[2] }]; #IO_25_15 Sch=cc set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { C[3] }]; #IO_L17P_T2_A26_15 Sch=cd set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { C[4] }]; #IO_L13P_T2_MRCC_14 Sch=ce set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { C[5] }]; #IO_L19P_T3_A10_D26_14 Sch=cf set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { C[6] }]; #IO_L4P_T0_D04_14 Sch=cg set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { DP }]; #IO_L19N_T3_A21_VREF_15 Sch=dp set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { E[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { E[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { E[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2] set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { E[3] }]; #IO_L19P_T3_A22_15 Sch=an[3] set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { E[4] }]; #IO_L8N_T1_D12_14 Sch=an[4] set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { E[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5] set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { E[6] }]; #IO_L23P_T3_35 Sch=an[6] set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { E[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7] 

Edit: Here is my stand (I don't know if this is correct):

 `timescale 1ns / 1ps module sim_TimeMUXDisplay(); reg [5:0]DIN; reg clk; wire [7:0]E; wire [6:0]C; wire DP; localparam [7:0]period=1; TimeMUXDisplay uut(clk,DIN,E,C,DP); initial begin clk=0; forever#(period/2.0)clk=~clk; end initial begin DIN=0; #period DIN=10; #period DIN=20; #period DIN=121; end endmodule 

And this is the graph that he creates:

And this is the circuit that Vivado creates with code:

Answer 1

Your test bench results are consistent with what you posted, you just selected the bad / useless test cases.

For `DIN = 10 => 0b001010, we get:

 Enb = DOUT[5] = DIN[5] = 0 DP = DOUT[0] = DIN[0] = 0 C = 0x7F since ENB=0 

Similarly, for DIN=20=>0b010100 we get:

 Enb = DOUT[5] = DIN[5] = 0 DP = DOUT[0] = DIN[0] = 0 C = 0x7F since ENB=0 

Finally, for DIN=121 = 57 =>0b111001 (121-64=57) we get:

 Enb = DOUT[5] = DIN[5] = 1 DP = DOUT[0] = DIN[0] = 1 C = 0x7F since DIN[4:1] = DOUT[4:1] = 0b1100 > 9 (default case) 

I modified your testbench and added some more useful cases (see http://www.edaplayground.com/x/4NYd ). If you look at the results for the last four prints ( DIN = 33 to 39), you will see that the C values ​​are what you would expect from this entry.

 DOUT, E, C, DP 0, 0b11111110, 0b1111111, 0 10, 0b11111110, 0b1111111, 0 20, 0b11111110, 0b1111111, 0 57, 0b11111110, 0b1111111, 1 33, 0b11111110, 0b1111110, 1 35, 0b11111110, 0b0110000, 1 37, 0b11111110, 0b1101101, 1 39, 0b11111110, 0b1111001, 1