Questions regarding NaN operations

Question

My SSE-FPU generates the following NaNs:

• When I perform any basic double operation, such as ADDSD, SUBSD, MULSD or DIVSD and one of both operands is NaN, the result is signed with the NaN operand and the lower 51 bits of the result mantissa are loaded with the lower 51 bits of the mantissa of the NaN operand.
• When both operations are NaN, the result is loaded with the destination register sign, and the lower 51 bits of the resulting mantissa are loaded with the lower 51 bits of the destination register before the operation. Therefore, the associative law is not taken into account when multiplying by two NaN operands!
• When I execute SQRTSD on a NaN value, the result has the sign of the NaN operand, and the lower 51 bits of the result are loaded with the lower 51 bits of the operand.
• When I do infinity multiplication with zero or infinity, I always get -NaN as a result (binary representation 0xFFF8000000000000u).
• If any operand is a NaN signal, the result becomes a quiet NaN if the exception is not masked.

Is this behavior defined in the IEEE-754 standard?

Answer 1

NaN have a sign and payload are collectively referred to as information contained in NaN.
The whole point of NaNs is that they are “sticky” (maybe Monadic is the best term?), As soon as we have NaN in the expression, the whole expression evaluates to NaN.
In addition, NaNs are specially processed when evaluating predicates (for example, binary relations), for example, if a is NaN, then it is not equal to itself.

Point 1
From IEEE 754:

The dissemination of diagnostic information requires that the information contained in NaN is stored through arithmetic operations and floating point format conversion.

Point 2
From IEEE 754:

Each operation, including one or two input NaNs, none of which signal, should not raise an exception, but if a floating point result should be delivered, it should deliver a quiet NaN as the result, which should be one of the input NaNs.

A floating point operation has never been associative.
I think you were looking for the term “commutative,” though, since associativity requires at least three operands.

Point 3
See paragraph 4

Point 4
From IEEE 754:

Invalid operations: 1. Any operation for signaling NaN (6.2)
2. Addition or subtraction - subtraction of the value of infinity, for example, (+ INFINITY) + (-INFINITY)
3. Multiplication - 0 × INFINITY
4. Department - 0/0 or INFINITY / INFINITY
5. The remainder is x REM y, where y is zero or x is infinite. 6. The square root if the operand is less than zero. 7. Converting a binary floating-point number to an integer or decimal format when overflowing, infinity or NaN excludes the representation in this format, and this cannot be signaled otherwise
8. Comparison by predicates including <or>, without?, When the operands are disordered (5.7, table 4)

Point 5
From IEEE 754:

Each operation associated with NaN signaling or invalid operation (7.1) should, if there is no trap, and if a floating point result is to be delivered, deliver a quiet NaN as the result.

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Due to its importance, the IEEE 754 standard can be found here .