The company I currently work with uses several IDEs (they develop firmware for various embedded platforms). All of their C projects use a Makefile, so we decided to also add rules to our default Makefile to run static code analysis tools.
One of the IDEs they use is Eclipse. Here we added additional targets to the Make Target view, which runs the lint target from the Makefile, for example. Since we use several IDEs, we can specify the tools created by the Makefile to generate a specific result for the IDE used. For Eclipse, we do this by setting up the build command and adding something like IDE_ENV=eclipse to the end. This works great.
Recently, one of the engineers mentioned that it would be very useful if he could run tools, as defined in the Makefile, for a single file. So, I updated the Makefile, and now it takes the SOURCE_FILE variable with the path to the file to be checked.
In Eclipse, I tried adding SOURCE_FILE=${selected_resource_loc} and just SOURCE_FILE=${resource_loc} , but these variables do not seem to work when running Make Target. I also tried using $(selected_resource_loc) and $(resource_loc) directly in the Makefile, but with no luck.
Can someone tell me how I can transfer the currently selected Make file when launching a target from the Make Target view?
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