The relationship between instruction pipelines and instruction loops

Question

I understand the basic principle of pipelining instructions .

I also understand that some instructions may take longer ( loops per instruction ).

But I do not get the connection between both.

All piping diagrams, which, as I see it, seem to be “perfect” instructions, they all have the same length (number of cycles).

But what if the first instruction executes 5 cycles and the second takes 3 cycles? Does the processor support two cycles?

Will this stall be called bubble ? Or is it different from the dangers and dependencies of the data?

Also, does the length of the instruction in bytes matter?

Answer 1

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Answer 2

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