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Assembler GNU Arm changes ORR to MOVW

I am compiling the following assembler fragment:

.syntax unified
.cpu cortex-m4
.thumb

.section  .text

orr r1, #12800
orr r1, #12801

Essentially just two OR instructions. If I look at the results with objdump, I get:

bla.o:     file format elf32-littlearm


Disassembly of section .text:

00000000 <.text>:
   0:   f441 5148   orr.w   r1, r1, #12800  ; 0x3200
   4:   f243 2101   movw    r1, #12801  ; 0x3201

Second OR silently changed to MOVW! The assembler ran as follows: arm-none-eabi-gcc -g -Wall -c bla.sand it did not show any warnings.

Version as- GNU assembler version 2.29.51 (arm-none-eabi) using BFD version (GNU Tools for Arm Embedded Processors 7-2017-q4-major) 2.29.51.20171128running on OSX.

Any idea why the second OR is changing in MOV?

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2 answers

The gas team confirmed that this was a mistake and checked in the patch. The Bugzilla entry can be found at https://sourceware.org/bugzilla/show_bug.cgi?id=22773

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source 
.syntax unified
.cpu cortex-m4
.thumb

.section  .text

orr r1, #12800
orr r1, #12801

arm-none-eabi-as -version GNU (GNU Binutils) 2.29.1 Copyright (C) 2017 Free Software Foundation, Inc. ; GNU General Public License 3 . . "arm-none-eabi".

arm-none-eabi-as so.s -o so.o
arm-none-eabi-objdump -D so.o

so.o:     file format elf32-littlearm


Disassembly of section .text:

00000000 <.text>:
   0:   f441 5148   orr.w   r1, r1, #12800  ; 0x3200
   4:   f243 2101   movw    r1, #12801  ; 0x3201

Jester , .

2,30 . .

2.27.1 2.28. tc-arm.c armv8m. (Cortex-m23 cortex-m33)

  /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
 UINT16 (T3 encoding), MOVW only accepts UINT16.  When
 disassembling, MOV is preferred when there is no encoding
 overlap.
 NOTE: MOV is using ORR opcode under Thumb 2 mode.  */
  if (((newval >> T2_DATA_OP_SHIFT) & 0xf) == T2_OPCODE_ORR
  && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m)
  && !((newval >> T2_SBIT_SHIFT) & 0x1)
  && value >= 0 && value <=0xffff)
{
  /* Toggle bit[25] to change encoding from T2 to T3.  */
  newval ^= 1 << 25;
  /* Clear bits[19:16].  */
  newval &= 0xfff0ffff;
  /* Encoding high 4bits imm.  Code below will encode the
     remaining low 12bits.  */
  newval |= (value & 0x0000f000) << 4;
  newimm = value & 0x00000fff;
}

ARM, 10 , , ​​ .

, ORR-, MOV, , , . , , MOV ORR. , , , MOV ORR, MOV-. .

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, , GCC , .

orr r1,#0x3200
orr r1,#0x0001

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cortex-m7

test.s

.cpu cortex-m7
.syntax unified
.thumb

.thumb_func
.globl test1
test1:
    orr r0,#0x3200
    bx lr

.thumb_func
.globl test2
test2:
    orr r0,#0x3201
    bx lr


hexstring(test1(0x0000));
hexstring(test2(0x0000));
hexstring(test1(0x00FE));
hexstring(test2(0x00FE));


arm-none-eabi-as --version
GNU assembler (GNU Binutils) 2.30


0800005c <test1>:
 800005c:   f440 5048   orr.w   r0, r0, #12800  ; 0x3200
 8000060:   4770        bx  lr

08000062 <test2>:
 8000062:   f243 2001   movw    r0, #12801  ; 0x3201
 8000066:   4770        bx  lr


00003200 
00003201 
000032FE 
00003201

A MOV - MOV, ORR.

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bada43421274615d0d5f629a61a60b7daa71bc15 tc-arm.c: 23596 - .

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