How to create a pseudo random number in FPGA?

Question

How to generate a pseudo random number in FPGA?

Answer 1

This has been reviewed (I would go for LFSR): Spartan-3E random number generation

Answer 2

There's a great note on the Xilinx application for generating pseudo-random number sequences efficiently in FPGA. This is XAPP052 .

Answer 3

(, ), .

It uses only exclusive and / or shear, so it is very simple to implement it at the hardware level.

Answer 4

As others have said, LFSR can be used for pseudo random numbers in FPGAs. Here is the implementation of VHDL 32-bit LFSR maximum length.

process(clk)

  -- maximal length 32-bit xnor LFSR based on xilinx app note XAPP210
  function lfsr32(x : std_logic_vector(31 downto 0)) return std_logic_vector is
  begin
    return x(30 downto 0) & (x(0) xnor x(1) xnor x(21) xnor x(31));
  end function;

begin
  if rising_edge(clk) then
    if rst='1' then
      pseudo_rand <= (others => '0');
    else
      pseudo_rand <= lfsr32(psuedo_rand);
    end if;
  end if;
end process;