The short answer is no, the type of the array does not map to the register.
Long answer: An
array type in VHDL is just an indexed collection of elements of the same type. In your case, you are probably using an array as the result of a register bank.
, , 8 , 16 . ( 8) 16- . :
component reg8x16
port(
clock: in std_logic;
reset: in std_logic;
enable: in std_logic;
rout : out r_array(0 to 7)
);
end component;
rout - . , 0 rout(0), std_logic_vector(15 downto 0).
, - ( ). :
type r_array is array (integer range <>) of std_logic_vector(15 downto 0);
(integer range <>) - , (, ).
, . , reg8x16. , 16- , std_logic_vector(15 downto 0); ( , ... VHDL). 8 reg8x16.
user285321