File Aliases

Question

Please explain $ @ $ ^ $ in the makefile below

LIBS = -lkernel32 -luser32 -lgdi32 -lopengl32 CFLAGS = -Wall # (This should be the actual list of C files) SRC=$(wildcard '*.c') test: $(SRC) gcc -o $@ $^ $(CFLAGS) $(LIBS) 

Answer 1

Here is what these two characters mean:

• $ @ is the target, i.e. test
• $ ^ - a list of prerequisites for the rule (in this case, an extended list of wild cards, as indicated in SRC=$(wildcard '*.c') )

All such variables are explained in the automatic variable page of the GNU manual.

Answer 2

 SRC=$(wildcard '*.c') 

This is just your original file name ending in .c ie file1.c, file2.c file3.c, etc.

at

 test: $(SRC) gcc -o $@ $^ $(CFLAGS) $(LIBS) 

$ - way to define variables in Makefile

$ @ is your goal, in your case it is a "test".

$ ^ - a list of all the prerequisites of the rule, including the names of the directories in which they were found

$ <- list of all dependencies

ref: https://www.gnu.org/software/make/manual/make.html#Automatic-Variables