First of all, sorry for my English.
I know that the architecture is very complex and there is a wide range of situations, but the general generalization is that computer architecture has 32-bit words, which means that registers, memory accesses and buses work with 32-bit words (but I think, there are many options in current architectures).
Well, let's say this is a rule, and our architecture is little continental, like x86. In this case, if we want to read short int (2 bytes long), the memory then reads the 4-byte word that contains our short . Suppose that the containing word W is 0xf1342ea0 , in memory:
{a0, 2e, 34, f1} // a0 is the byte in the lowest address.
and our half-layer H is in the upper part of W, then H is 0xf134. I understand that the processor receives a word with a shift of short from memory:
{34, f1, 00, 00}
since 0x0000f134 is equal to 0xf134.
Given this picture, since the processor has a length of 4 bytes, and therefore it is necessary, in any case, to shift, why is it necessary that 2-byte data be aligned in 2-byte word boundaries?
In other words:
Why it is encouraging not to read short 0xf134 in a word:
{ff, 34, f1, 0a}
?
EDIT . Another way to express the same doubt: why the definition of alignment
A object of size N and address d is aligned if d is divisible by N.
and not:
A object of size N and direction d is aligned respect to an architecture of B bytes if d is divisible by B, or ⌊d/B⌋ == ⌊(d+N)/B⌋ if N < B.
?
NOTE. . The property ⌊d / B⌋ == ⌊ (d + N) / B⌋ means that the object belongs to the aligned word.