Avoid double inclusion: preprocessor directive against makefiles

Question

I am working on the transition from Frankenstein and single-file programs to thousands of lines into well-structured and organized multi-file programs. Currently, what seems natural (naive) is to create a love triangle of headings for my three files:
file_1 includes file_2, file_4
file_2 includes file_3, file_4
file_3 includes file_1 .... etc. etc.
These files have variables, methods, structures, etc., which I need between other files.

And of course, I get double inclusion errors.

My question is: should these problems be avoided by using preprocessor directives in the headers (for example, including structures, methods, etc. entirely in the header), or should I compile using the makefile (which I hear can also be used to solve this problem, but I never did that)?

Answer 1

, .., - . Makefiles , . :

• shared variable extern ( .c)
• ( .c)

#IFNDEF #ENDIF, .c...

Answer 2

, . Makefile , .

, , .

Answer 3

"inv_tree.h"

#ifndef INV_TREE_H
#define INV_TREE_H
...
#endif

"inv_tree.h" , , INV_TREE_H "inv_tree.h". , "inv_tree.h",

Answer 4

, . , , .

, forward ( heder).

.

: , , head.