Explicitly determine how LUTs and fragments are used in the Xilinx XST tool?

Question

Explicitly determine how LUTs and fragments are used in the Xilinx XST tool?

I am trying to implement very specific LUT and slices behavior written in VHDL for FPGA Xilinx Virtex 5 synthesized using XST tools (s). I don’t know if I can achieve my behavior with the tools to conclude what I mean, since I can clearly do this?

I am talking about using 6-input LUTs on Virtex5, of which 4 of them are in CLB.

I want to explicitly indicate: - The inputs for each of the 4 LUTs in the ONE CLB slice - Route the outputs 'S' from 4 XORCYs - Indicate INPUT 'first' MUXCY (C0) - Route OUTPUT "4th" MUXCY (Cn) - Be able to indicate the inputs of each CLB LUT are in a specific order, since they are obviously cascaded.

Ideally, I would just like to create a "CLB" in VHDL with all the inputs and outputs and be able to display them.

I studied the documentation pretty hard and found nothing.

+5

vhdl xilinx fpga

Nektarios Mar 2 '11 at 3:05

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3 answers

Saar suggests using LUT6 to explicitly create a LUT. I prefer to control technology mapping with a LUT_MAP restriction. This requires less maintenance, and your HDL code remains compatible with your device and simulator.

Here is an example.

(* LUT_MAP="yes" *)
module mux4(sel, a, b, c, d, o);
input [1:0] sel;
input       a;
input       b;
input       c;
input       d;
output reg  o;

always @* begin
    case(sel)
    2'b00: o <= a;
    2'b01: o <= b;
    2'b10: o <= c;
    2'b11: o <= d;
    endcase
end
endmodule

(XST), ( 6-, ) LUT. KEEP_HIERARCHY RLOC, RPM ( ).

(* KEEP_HIERARCHY="true" *)
module mux4x4p4(sel, a, b, c, d, o);
input  [1:0] sel;
input  [3:0] a;
input  [3:0] b;
input  [3:0] c;
input  [3:0] d;
output [3:0] o;

(* RLOC="X0Y0" *)
mux4 m0(sel, a[0], b[0], c[0], d[0], o[0]);
(* RLOC="X0Y0" *)
mux4 m1(sel, a[1], b[1], c[1], d[1], o[1]);
(* RLOC="X0Y0" *)
mux4 m2(sel, a[2], b[2], c[2], d[2], o[2]);
(* RLOC="X0Y0" *)
mux4 m3(sel, a[3], b[3], c[3], d[3], o[3]);
endmodule

RPM datapaths - www.fpgacpu.org. , " FPGA": http://www.fpgacpu.org/log/aug02.html#art

!

+6

Jan Gray 08 '11 15:32

, RLOC BEL. VHDL:

VHDL Syntax

Declare the VHDL constraint as follows:
attribute bel : string;

Specify the VHDL constraint as follows:
attribute bel of {component_name| label_name}: {component|label} is {F|G|FFA|FFB|FFC|FFD|FFX|FFY|XORF|XORG|A6LUT|B6LUT|C6LUT|D6LUT|A5LUT|B5LUT|C5LUT|D5LUT}";