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Safeguards for streamlining memory and good programming practice

Regarding the ordering described below, I have some related questions.

  • Given these order guarantees, in many places I don’t need explicit fences. However, how can I express the "fence" of the compiler, in particular GCC? That is, the guarantee for the execution of the program is applied only on condition that the optimizer does not change the order of my program.

  • Are there general / popular new chips that have general purpose cores that do not offer such guarantees?

  • I am a bit confused in C ++ 0x with the idea of ​​interleaving. Should I use the "atomic" class to use these guarantees or is there some other aspect in the project that also makes it possible to use these guarantees?

Memory order

Both Intel and AMD, at least with x86_64, ensure that memory loading is consistent with storage operations performed on a single processor. That is, if any processor runs these stores:

  • Save A <- 1
  • Save B <- 2
  • Save C <- 3

At that moment, when any other processor sees C (3), it is also guaranteed to see the previous stores A (1) and B (2). Now, visibility between processors can alternate, but the storage order from any given processor will also be sequential.

They also have transitive guarantees when processor 0 reads the value stored in processor 1, and then writes the value that processor 2 reading the new value should also see this value from Processor 1.

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SMP . Linux , . memory-barriers.txt.

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, - , , . ++ 0x :

  • - std::mutex
  • - std::atomic<T>
  • - std::atomic_thread_fence.

The last two allow a memory order parameter that provides additional flexibility (only for experts!) On platforms that do not guarantee consistent consistency, but this does not apply to x86.

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