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Disabling Team Consolidation (CCC) in SATA AHCI

I am working on kernel version 2.6.35.9 and am trying to disable command pooling.

The output is lspcishown below:

00:00.0 Host bridge: Intel Corporation 82P965/G965 Memory Controller Hub (rev 02)
00:01.0 PCI bridge: Intel Corporation 82P965/G965 PCI Express Root Port (rev 02)
00:19.0 Ethernet controller: Intel Corporation 82566DC Gigabit Network Connection (rev 02)
00:1a.0 USB Controller: Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #4 (rev 02)
00:1a.1 USB Controller: Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #5 (rev 02)
00:1a.7 USB Controller: Intel Corporation 82801H (ICH8 Family) USB2 EHCI Controller #2 (rev 02)
00:1c.0 PCI bridge: Intel Corporation 82801H (ICH8 Family) PCI Express Port 1 (rev 02)
00:1c.4 PCI bridge: Intel Corporation 82801H (ICH8 Family) PCI Express Port 5 (rev 02)
00:1d.0 USB Controller: Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #1 (rev 02)
00:1d.1 USB Controller: Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #2 (rev 02)
00:1d.2 USB Controller: Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #3 (rev 02)
00:1d.7 USB Controller: Intel Corporation 82801H (ICH8 Family) USB2 EHCI Controller #1 (rev 02)
00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev f2)
00:1f.0 ISA bridge: Intel Corporation 82801HH (ICH8DH) LPC Interface Controller (rev 02)
00:1f.2 RAID bus controller: Intel Corporation 82801 SATA RAID Controller (rev 02)
00:1f.3 SMBus: Intel Corporation 82801H (ICH8 Family) SMBus Controller (rev 02)
01:00.0 VGA compatible controller: nVidia Corporation G72 [GeForce 7300 LE] (rev a1)
04:03.0 Mass storage controller: Promise Technology, Inc. PDC20268 (Ultra100 TX2) (rev 02)

My disks have Native Command Queuing enabled.

I watched the Serial ATA AHCI 1.3 Specification and found on page 115 that -

The CCC function is only used if CCC_CTL.EN is set to '1. If CCC_CTL.EN is set to "0", interrupts must be generated by CCC.

( , AHCI) , . enum HOST_CAP_CCC = (1 << 7) drivers/ata/ahci.h, , , .

- , CCC ? !

gby:

, 64 . 64 128 ( = 512 ).

, :

Timestamp  | Timestamp  |  Difference 
   at      |     at     |  in microsecs
Sector 255 - Sector 127 =  510
Sector 383 - Sector 255 =  3068
Sector 511 - Sector 383 =  22
Sector 639 - Sector 511 =  22
Sector 767 - Sector 639 =  12
Sector 895 - Sector 767 =  19
Sector 1023 - Sector 895 =  13
Sector 1151 - Sector 1023 =  402

, , -, , , , .

, hdparm.

, , , .

UPDATE: , .

bio __make_request() . 2560 .

, , do_IRQ(). , blk_complete_request(). , (.. , ). struct bio blk_complete_request() __make_request() . ( T_0). , ( T_1). - T_1 - T_0 - 1 . , - T_1 - T_0. , 350 , 1,2 2560 .

. , .

, , , , , T_1 - T_0 ( < 1 ).

Serial ATA AHCI 1.3 (. 114) , :

, , .

, , 1 . CCC.

- , . stackoverflow? , ...

: WD Caviar Black ( - WD1001FALS).

-?: - (

+5
1

AFAIK, HBA capabilities bit7(CCC supported) - RO, , , CCC. CCC, CCC_CTL.EN, RW

, ?

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