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VHDL: Is it possible to define a common type with records?

I am trying to define a complex type (i.e. a type that consists of real and imaginary parts), and I am trying to find a way to make it general.

This my current static code:

  type complex_vector is record
    Re : signed(15 downto 0);
    Im : signed(15 downto 0);
  end record;

Now I wonder if there is a way to do this generic, in another word something like:

  type complex_vector (Generic: Integer := WIDTH) is record
    Re : signed(WIDTH downto 0);
    Im : signed(WIDTH downto 0);
  end record;

I tried google for the solution as well as through my books, but I can not find any solution. Really no? Without entries, you can snatch something like this:

type blaaa is array (NATURAL range <>) of STD_LOGIC;

Thanks for any input.

EDIT:

Or could I do something like the following?

type complex_primitives is (re, im);
type complex_vector is array (re to im) of signed(natural range <>);

The compiler complains though ..

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2 answers

The following is the legal syntax in VHDL-2008:

type complex is record
  re : signed ;  -- Note that this is unconstrained
  im : signed ;
end record ;

signal my_complex_signal : complex (re(7 downto 0), im(7 downto 0)) ;

. . VHDL-2008 . VHDL-2008, .

VHDL-2008 , . , .

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, VHDL-2008 ( !) ...

, , , , , , , .

-- complex_vector_16.vhd
package types is
  type complex_vector is record
    Re : signed(15 downto 0);
    Im : signed(15 downto 0);
  end record;
end;

-- complex_vector_32.vhd
package types is
  type complex_vector is record
    Re : signed(31 downto 0);
    Im : signed(31 downto 0);
  end record;
end;


library complex.types
use complex.types.complex_vector;

, complex_vector , !

/ . , VHDL-2008.

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