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My task is to write a 16-bit ALU to verilog. I came across difficulties when I perform a role that should rotate the operand and make addition and subtraction from 2 additions. I know how to work with paper and pencil, but I can not find ways to do this in Verilog. for example: A is denoted as a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 if I am going to rotate 4 bits, the answer will be a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 a15 a14 a13 a12

I tried concatenation but turned out to be wrong. you need help ...

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Why is concatenation wrong? That should do what you ask.

 assign A_out[15:0] = {A_in[11:0], A_in[15:12]};
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:

assign A_out = {A_in,A_in} >> (16-shift[3:0]);

shift 0, A_in. shift A_in MSB A_in.

, , . 16- barrel shifter 4 2 1.

wire [15:0] tmp [3:1];
assign tmp[3] = shift[3] ? {  A_in[ 7:0],  A_in[15: 8]} : A_in;
assign tmp[2] = shift[2] ? {tmp[3][11:0],tmp[3][15:12]} : tmp[3];
assign tmp[1] = shift[1] ? {tmp[2][13:0],tmp[2][15:14]} : tmp[2];
assign A_out  = shift[0] ? {tmp[1][14:0],tmp[1][15   ]} : tmp[1];
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assign A_out = A_in << bits_to_rotate;

bits_to_rotate ( , ). , . .

, . , :

assign A_out = (A_in << bits_to_rotate) | (A_in >> ~bits_to_rotate);
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- . 8- 1- (8'b00001111 << 1), 8'b00011110) , 9 (8'b00001111 << 9), , 8'b00011110, 17 , :

PATTERN_TABLE

, , , 1 (1,9,17,25... 249), 001 (1).

, 6 (6,14,22,30... 254), 110 (6).

, (8'b00000111), , :

reg_out_temp <= reg_in_1 << (reg_in_2 & 8'h07);

reg_out_temp must be double reg_in_1, in this case there reg_out_temp must be 16 bits and reg_in_18 bits, so you can get the bits to be transferred to another byte when you transfer the data so that they can be combined using the OR expression:

reg_out <= reg_out_temp[15:8] | reg_out_temp[7:0];

So, in two measures you get the result. For 16-bit rotation, your mask should be 8'b00011111( 8'h1F), because your shifts go from 0 to 16, and your temporary register should be 32 bits.

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