Does the synthesizer support one or two processes?

Question

There are two popular ways to encode a state machine in VHDL: one process or two processes. Rumor has it (and in some colleges) that two processes can lead to better equipment. Does anyone have strong evidence of this? My own preliminary tests show that there is no difference.

I am looking for reproducible experiments: VHDL code for two coding styles and features of their synthesis (which tool, which parameters).

Please help me expose or confirm the myth that the two processes lead to better synthesized equipment.

Answer 1

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Answer 2

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Answer 3

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//Instances 1 clock gate
reg [7:0] value;
always @(posedge i_clk)
  if(enable)
    value <= new_value; 

//Instances 8 muxes
always @(posedge i_clk)
  if(enable)
    value <= new_value;
  else //Exhaustive so assignment always occurs
    value <= value;

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