The correct way to detect signal edges in Verilog

Question

I want to detect the leading edge of the signal from the trigger AAtoBB

                    +----+
  A ----------------|    |----- OUT
        +----+      | BB |
  B ----|    |------|>   |
        | AA |      +----+
clk ----|>   |
        +----+

Verilog Code:

    module edge_detect (
        input A,
        input B,
        input clk,
        output OUT
    );

        reg AA;
        reg BB;

        always @(posedge clk) begin
            AA <= B;
        end

        always @(posedge AA)begin
            BB <= A;
        end

        assign OUT = BB;
    endmodule

The conclusion is AAused as a clock for BB, saying that he AAcompleted his task, and then BBcan now continue his work.

I rarely see this code. Is this a good practice?

If not, is there another way to detect the edge of the signal?

Answer 1

People tend to frown on using data as a watch for various reasons.

Personally, if I wrote this, I would go with:

module edge_detect (
    input A,
    input B,
    input clk,
    output OUT
);

    reg AA;
    reg BB;
    wire enA;

    always @(posedge clk) begin
        BB <= B;
    end

    assign enA = !BB && B;

    always @(posedge clk)begin
       if (enA) begin
            AA <= A;
      end
    end

    assign OUT = AA;
endmodule

                                +----+
  A ----------------------------|D   |----- OUT
                     +---+      | AA |
      /--------------|   |      |    |
      | +----+       |AND|------|E   |
  B ----|    |------o|   |      |    |
        | BB |       +---+      |    |
clk ----|>   |          clk ----|>   |
        +----+                  +----+

The behavior is a little different though.