When L1 passes are much different from L2 access ... associated with TLB?

Question

I performed some tests on some algorithms and profiled their usage and memory efficiency (access L1 / L2 / TLB and omissions), and some of the results are quite intriguing to me.

Given the inclusive cache hierarchy (L1 and L2 caches), should the number of L1 cache misses coincide with the number of access to L2 caches ? One of the explanations that I find will be related to the TLB: when the virtual address does not appear in the TLB, the system automatically skips the search in some cache levels. Does this sound legal?

Answer 1

First, inclusive cache hierarchies may not be as widespread as you expect. For example, I don’t think that any modern Intel processors - not Nehalem, not Sandybridge, maybe Atoms - have L1, which is included in L2. (Nehalem and probably Sandybridge do, however, have L1 and L2 included in L3, using current Intel, FLC, and MLC terminology in LLC.)

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Answer 2

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