Multidimensional Array of Signals in VHDL

Question

I have a signal in VHDL declared as follows:

signal Temp_Key : std_logic_vector(79 downto 0);

This one Temp_Keyis transmitted through the cycle for31 times and changes. I want to store all 31 different Temp_Keysin an array.

Can multidimensional arrays be used in VHDL to store 80-bit signals?

Answer 1

Yes, first you need to declare a type:

type YOUR_ARRAY_TYPE is array (0 to 30) of std_logic_vector(79 downto 0);

Note. You can also declare a type of length undefined so that you can specify how many 80 bit words it has when you declare your signal. And with VHDL 2008 you can also leave the slv size unspecified, also be declared when creating your signal. For instance:

type slv_array is array (natural range <>) of std_logic_vector;

and then use it

signal MY_SIGNAL : YOUR_ARRAY_TYPE;
...
MY_SIGNAL(0) <= data;
...
MY_SIGNAL(1) <= data;

See here for reference.

Answer 2

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Answer 3

VHDL has two options

Option 1

signal X is array (range) of ArrayType;

Option 2

signal Y is array (range1, range2) of Type;

I think option 1 is better supported by tools. I also found a similarity between the two options and functional programming, which teaches us that we can always curry a multidimensional function (x, y) into a one-parameter chain, f (x) → f (y). The latter looks like an array of arrays.