What is the meaning of a “simple” starting block?

Question

I read a third-party Verilog and found this:

function [31:0] factorial;
    input [3:0] operand;
    reg [3:0] index;

    begin
        factorial = operand ? 1 : 0;
        for(index = 2; index <= operand; index = index + 1)
        factorial = index * factorial;
    end
endfunction

It seems that the keywords beginand endare redundant. They are? What is their use?

Answer 1

I do not know about the general case, but in this particular case:

If a function contains more than one statement, the statements must be
enclosed in a begin-end or fork-join block. 

Source: Verilog Golden Reference Guide

Answer 2

. Verilog , . SystemVerilog-2005, - , . -, endfunction/endtask. ! , , endtask/endfunction, ? . SystemVerilog!

- - Verilog SystemVerilog Guru

Answer 3

SystemVerilog ( IEEE 1800-2009) / function. ( ..) , 2005 .