Geek Answers Handbook

Direct Mapped Cache Hit / Miss

We apologize if this is the wrong stackexchange for this; it just seemed the closest to a place that could help in computer architecture. For a home problem in computer systems, they asked me:

Consider three direct mapped caches X, Y, and Z each interpreting an
8-bit address slightly differently according to the {tag:setIdx:byteOffset}
format specified. For each address in the reference stream, indicate whether the
access will hit (H) or miss (M) in each cache.

                  C1       C2     C3
Address Formats: {2:2:4} {2:3:3} {2:4:2}

Address References in Binary: 00000010, 00000100...

I have to say whether each of the address links will result in a hit or skip, but I don't know where to start.

For formats, I thought that the tag means the data tag in the cache block, setIdx means the number of bits set to represent the various blocks in the cache, and the offset is a specific byte in the block that you can choose from.

I think I don’t understand what a hit or miss is. I thought that there are 3 types: mandatory, potential, and conflict. How do I know what is a mandatory error if I don’t know what is already in the cache? How can I specify cache capacity based on tag formats?

Thanks for any tips or advice.

+5
source share
2 answers

Take C1, for example, it has 2 bits for setIdx and 4 bits for byteOffset.

Thus, this cache will have 2 ^ 2 = 4 blocks (00, 01, 10 and 11), and each block will have 2 ^ 4 = 16 bytes.

Now the address link can be divided into C1 format: {00 00 0010}

Assuming the cache is empty by default, the first search will result in a miss. However, the cache will now have a “00” block loaded with the “00” tag.

{00 00 0100} "00", , "00", .

+3

, . , 00 00 0100 , . - . , . , . 00 00 0100 00 00 0100, .

, , , .

( / ) mod ( )

+1

More articles:


All Articles