The verilog operator "~" additionally gives an undesirable result

Question

In the following simplified Verilog code:

wire [31:0] depth; wire mode_u2 = 1'h0; assign depth = 'h80 + (~mode_u2); 

if I do a depth mapping and simulate it using VCS (2014.12-1)

 $display("depth is 0x%2x", depth); 

I get 0x7f instead of the expected 0x81 . ~ Mode_u2 seems to be seen as minus 1.

If I changed ~mode_u2 to !mode_u2 . I get 0x81 as expected.

which is more interesting if I do wire mode = ~mode_u2 and then assign depth = 'h80 + (~mode) instead of 0x80 , I get 0x7e

Am I missing something?

Can someone explain why ~ behaves this way in operation + ? Or is it one of those simulators and syntheses that are different from each other?

Many thanks!

Willie

Answer 1

The operands of the add operator must be expanded to the size of the left side (or the maximum width of the two operands, depending on the context) before the addition is performed.

In this case, mode_u2 needs to be increased to 32 bits. I could not find a link for this, but it seems that the bit extension takes precedence over the ~ operator. It means:

 depth = 'h80 + (~mode_u2) = 32'h0000_0080 + (~32h0000_0000) = 32'h0000_0080 + 32'hffff_ffff = 32'h0000_007f 

The result of the operator ! , however, by definition, it’s one bit, and I assume that bit expansion occurs twice:

 depth = 'h80 + (!mode_u2) = 32'h0000_0080 + (!32'h0000_0000) = 32'h0000_0080 + 1'h1 = 32'h0000_0080 + 32'h0000_0001 = 32'h0000_0081 

Similarly for mode :

 depth = 'h80 + (~mode) = 32'h0000_0080 + (~32'h0000_0001) = 32'h0000_0080 + 32'hffff_fffe = 32'h0000_007e