How is a sign flag computed with imul?

Question

The documentation for imul states that:

SF is updated according to the most significant bit of the result with the truncated operand size in the receiver.

For a 64-bit operation, I understand that SF = (a * b) >> 63 , or easier if a and b signed, SF = a * b < 0 .

However, I get an unexpected result that multiplies two large numbers:

 mov rax, 0x9090909090909095 mov rdx, 0x4040404040404043 imul rax, rdx 

The result 0x9090909090909095 * 0x4040404040404043 is 0xefcba7835f3b16ff . It has the sign bit set, however the SF flag is cleared after the imul . What's happening?

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It was cross-posted on Intel forums some time ago.

Answer 1

Other sources say SF is undefined after imul . This most likely means that the SF result is well defined on new processors, but older ones do not offer this feature. My computer is 5 years old, I probably fall with the second category.

EDIT : using the Archive.org Wayback Machine, I found that the documentation has changed, indicating that SF undefined for SF was defined in September 2014 . The previous version, June 2014, still says SF is undefined. This is described in the accompanying Documentation Changes , although there is no justification for this change.

EDIT 2 My processor is an i7 M 620. I had access to an even earlier Core2Duo P7550 and was able to confirm that imul does not install SF on it.

EDIT 3 Starting with the September 2016 release, imul says SF is undefined, so this fixes the problem.