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Get internal vhdl design cues in ncvhdl (alternative modelsim signaling spy)

In ModelSim you can use something like

in models, we can use init_signal_spy ("../.../sig", mysignal);

to get deep hierarchical signals. Is there a way to get these signals using Cadence NCVhdl?

This should be marked with "SimVision", which is the name of the tool, but this flag does not seem to exist.

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If Cadence tools support VHDL-2008, you can access signals, common variables or constants at other levels of your design using external names.

Direct use is as follows.

A <= <<signal .tb_top.u_comp1.my_sig : std_logic_vector >>;

Please note that the object must be designed before the link . Since VHDL projects are developed on an instantiation basis, subsequent projects may refer to earlier ones.

Use an alias to create a local short hand name:

 alias u1_my_sig is <<signal u1.my_sig : std_logic_vector >>;

The path begins with:

  • "= the path starts at the top level:". tb_top.my_sig "
  • "u1" = the path starts at the current level: "u1.my_sig"
  • "^" = the path starts from a level above the current: "^ u2.my_sig"
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As you can see here , the function is called nc_mirror .

  nc_mirror (destination => "destination", source => "source", verbose => "verbose");

The destination and source are required and does the same as init_signal_spy for modelsim. The third parameter is optional. In addition, it supports mirroring arrays or records.

This interesting answer provides a shell package that converts nc_mirror or init_spy_signal (and others) to the probe function.

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