How does an Intel processor access the Branch Trace Store storage buffer?

Question

The Intel processor has a Branch Trace Store (BTS) function, recording branches and storing them in a buffer specified by the user / program. In fact, I wonder if the processor processes the BTS buffer through the MMU (page table) or just physically accesses the BTS buffers?

Answer 1

From Intel Manual Volume 3, Chapter 17.4.9 (BTS and DS Save Area) image for a 32-bit version of debug storage

The base base of BTS . The linear address of the first byte of the BTS buffer. This address should point to the natural boundary of the double word.

and for IA32_DS_AREA MSR

Write the base linear address of the DS buffer management area in MS32 IA32_DS_AREA.

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In general, each address that you set for the processor is a linear address, so it does not depend on the installed segments, and therefore paging occurs only if activated.
Of course, this is true only where it does not create a recursive dependency, for example, with the CR3 register.

To answer your question: if paging is activated, then the specified address is converted, otherwise it is used as is.