Variable number of inputs and outputs in VHDL

Question

I have to create an object in VHDL that has a variable number of inputs and outputs. This number of contacts must be specified in the GENERIC design. Assume this code:

entity HELLO is GENERIC(NUM_INPUT: integer:=4; NUM_OUTPUT: integer:=2 ); port( input1 : in std_logic_vector(31 downto 0); input2 : in std_logic_vector(31 downto 0); input3 : in std_logic_vector(31 downto 0); input4 : in std_logic_vector(31 downto 0); out1 : out std_logic_vector(31 downto 0); out2 : out std_logic_vector(31 downto 0) ); end entity HELLO; 

Obviously, writing them manually (as in the example above) makes the GENERIC construct useless.

I want these 4 inputs and 2 outputs to be automatically generated according to the GENERIC information. How to make?

Answer 1

I think the easiest way to achieve this is to define a custom array type for your 32-bit word in a package, for example:

 type WORD_ARRAY_type is array (integer range <>) of std_logic_vector (31 downto 0); 

declaring your entity then becomes:

 use work.HELLOPackage.all; entity HELLO is GENERIC ( NUM_INPUT : integer := 4; NUM_OUTPUT : integer := 2 ); port ( input1 : in WORD_ARRAY_type(NUM_INPUT-1 downto 0); out1 : out WORD_ARRAY_type(NUM_OUTPUT-1 downto 0) ); end entity HELLO; 

You can also use unlimited arrays for input and output:

 entity HELLO is GENERIC ( NUM_INPUT : integer := 4; NUM_OUTPUT : integer := 2 ); port ( input1 : in WORD_ARRAY_type; out1 : out WORD_ARRAY_type ); end entity HELLO; 

then work with these ports using generics. When instantiating an object, simply connect the array with the correct dimensions to match the generics.