What is the TSX Skylake errata SKL-105 related status?

Question

As you know, Intel had to disable TSX in Haswell series processors through microcode updates. This was due to an error in the TSX implementation, which could give erroneous results if these instructions were used.

What seems less well-known is that there also seem to be bugs affecting TSX on the new Skylake architecture. In particular, the “SKL-105” errors mentioned here:

http://www.intel.com/content/www/us/en/processors/core/desktop-6th-gen-core-family-spec-update.html

It specifically states that using TSX can lead to unpredictable system behavior. However, he also notes that the BIOS may perform the fix. However, the question arises of what this fix is. Does TSX turn off altogether, as a “fix” Haswell chip? Googling "SKL105" does not give any results, so it seems that the community does not know about it at all?

Some users have noticed that the TSX function is disabled "steatily" (but does not seem to know about the errors above):

https://www.reddit.com/r/hardware/comments/44k218/intel_disables_tsx_transactional_memory_again_in/

It is strange if only certain processor variants are affected, since it can be assumed that they will all have the same microarchitecture and, therefore, will be equally affected by this error.

By the way, another way to “fix” the microcode could work and which could be even more secretive: I believe it would be possible to update the microcode, which would still expose the presence of TSX (which seems like the function was still enabled), but will override implementing new TSX instructions using "dummy implementations" that will never actually break locks and, in fact, simply execute code in the old-fashioned way, thereby avoiding errors, but also refuse to improve performance, which may suggest TSX. The only way to determine if this has happened is to measure performance.

Does anyone have more information about TSX status on Skylake? In any case, it is strange that no more information is released, and you need to guess what is affected and what is not. And indeed, if the function is safe to use.

I have a 6700K and the function still exists. But it also depends on whether the BIOS manufacturer took the microcode updates, and also I did not actually evaluate the performance, so I can not exclude that it can still be disabled by cf. previous paragraph

Answer 1

As far as I know, it is supposedly fixed in the latest updated microcode update package from 2016-07-14. For Skylake, this will be a 0x9d / 0x9e revision of the base Skylake microcode (processor signatures 0x406e3 and 0x506e3).

This new TSX erratum seems to be present on Broadwell. I guess it was also fixed with the new Broadwell- * microcode update series, which were published along with the new Skylake microcode updates.

For Linux, which updates the microcode through the data sent by the bootloader, it is trivial to apply the update, and it is already available in most (serious) distributions. For Windows, you need to pester the system provider to update the EFI / BIOS.

Sorry, I don’t have the tools to test TSX in the latest Skylake / Broadwell microcode to see if it is blocking or “always crashing”. Regarding disabling TSX, you should understand that this has a real impact on L3 performance (it does not come for free!) And power consumption, it would be very useful to disable TSX BIOS on anything with a smaller L3.

Interestingly, the TSX chicken information is not publicly available, we have no idea how to disable (or enable it again).