Uvm_event and verilog system event difference

Question

What is the advantage of uvm_event over SystemVerilog event ? Can someone explain with a little pseudo-code?

Answer 1

UVM is nothing more than a wrapper library developed by SystemVerilog. Thus, the uvm_event and SystemVerilog events uvm_event same, but uvm_event has some additional features.

From the link to the UVM class :

The uvm_event class is a wrapper class around the SystemVerilog event construct. It provides some additional services, such as setting up callbacks and maintaining the number of waiters.

The traditional Systemverilog event does not have the functionality to transmit data when an event is triggered. So far, uvm_event adds this functionality. That way, you can pass a handle to the transaction class when an event is fired.

Like traditional SV events, uvm_event also has trigger and persistent trigger modes (whereas SV has wait(ev.triggered) and @(ev) ).

You can also add callbacks each time the event fires. This is done by registering a callback class with a specific event.

As for events, they seem expensive in terms of overhead. You can get many examples on uvm_event , like this one .

Answer 2

There are no advantages to using uvm_event over what is in the basic construction of the SystemVerilog event unless you need the extra features provided by uvm_event . Additional features include adding a uvm_object to be associated with the trigger, and booking information, such as tracking the number of waiters and the last time uvm_event was launched.

I did not see much benefit for these additional functions, and events in general are usually too low for most test stands.