Why processors do not have asymmetric registers?

Question

All processor architectures I came across have symmetrical registers, that is, the value you are reading is the value you wrote.

Is there a case for 16-bit register-limited instructions to have asymmetric registers?

eg.

• Registers 0-6 are "local" to the function call. The value recorded in this function call is the value to be read. Each function call level has its own registration hardware, so local registers are implicitly stored.
• Registers 7-9 are "global", possibly "streaming local" on the SMP processor.
• The values ​​recorded in the "call" registers 10-13 do not affect what is read from them in the context of the function call.
• The values ​​read from the "call" registers 10-13 are the values ​​recorded in the calling function, that is, the arguments of the function register are immutable.
• The values ​​written to the return registers 14-15 do not affect the fact that whet is read from them in this context of the function call.
• The values ​​read from the "return" registers 14-15 are the values ​​recorded in the function that has recently returned to the current function.

Each function level register has its own equipment, which only stacks when the call depth exceeds hardware.

(local) (global) ( call ) (ret) global regset 07 .. 09 . . . . | | ^ ^ . vv | | regsetN-1 00 .. 06 10 .. 13 14 15 |^ |^ | | ^ ^ v| v| vv | | fnN-1 RW RW RW RW RW RW | | ^ ^ vv | | regsetN 00 .. 06 10 .. 13 14 15 |^ |^ | | ^ ^ v| v| vv | | fnN RW RW RW RW RW RW | | ^ ^ vv | | regsetN+1 00 .. 06 10 .. 13 14 15 |^ |^ | | ^ ^ v| v| vv | | 

Will such a scheme reduce the pressure of the register in each function call with two or more registers?

I do not expect this to be a new idea, but I am interested in whether this was done, and if not, why not? If this is not a crazy idea or already done, I can implement this on an FPGA processor.

Is it too complicated to cost case-saving?

Are llvm difficulties the main reason that this is not done?

PS I know that superscalar processors are already much more complicated than schemes with renaming registers, etc. I'm just thinking about microcontroller class architectures.

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Update: It looks like the SPARC architecture did this. Why was this not useful for later ISA designers?

When the procedure is called, the register window is shifted by sixteen registers, hiding the old input registers and old local registers and making the old output registers new input registers.

Answer 1

This is how the SPARC registration windows worked. Although this looks like a good idea in isolation, interacting with the rest of the system reduces overall system performance.

From http://ieng9.ucsd.edu/~cs30x/sparcstack.html

It was an idea, anyway. The disadvantage is that when interacting with the system, the registers must be flushed onto the stack, which requires a long sequence of write operations to the data memory, which is often mainly garbage. Registering windows was a bad idea, which was triggered by simulation studies that examined only isolated programs, as opposed to multitask workloads, and considered compilers with poor optimization. It also caused significant problems when deploying high-performance Sparc processors such as SuperSparc, although later implementations have effectively handled the hurdles. The registration window is now part of the legacy of compatibility and is not easily removed from the architecture.