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VHDL port mapping issue

I am relatively new to VHDL. I am trying to write code to do unsigned multiplication using a combination of full adders. When compiling, it switches to port mapping. I resolved the errors on the first map, but all the other problems.

I get the same error for everyone: "The validity of the expression in the port map aspect must be static"

Here is my code. Any help is appreciated. Also, if you have general advice based on a look at my code, I would be grateful.

Thanks Buzkie

library ieee; use ieee.std_logic_1164.all; entity fulladder is port (a, b, c: in std_logic; sout, cout: out std_logic); end fulladder; architecture behav of fulladder is begin sout <= (a xor b) xor c ; cout <= (a and b) or (c and (a xor b)); end behav; library ieee; use ieee.std_logic_1164.all; entity unsignedmult is port (a,b: in std_logic_vector (3 downto 0); pro: out std_logic_vector (7 downto 0)); end unsignedmult; architecture synth of unsignedmult is --Declarations signal c1,c2,c3,c4,c5: std_logic_vector (3 downto 0); signal s1,s2,s3,s4: std_logic_vector (2 downto 0); component fulladder port (a,b,c:in std_logic; sout,cout:out std_logic); end component; begin --Row 0 ----Sin-----A&B-------Cin--Sout---Cout Fand00: fulladder port map('0',(a(0) and b(0)),'0',pro(0),c1(0)); Fand01: fulladder port map('0',(a(1) and b(0)),'0',s1(0),c1(1)); Fand02: fulladder port map('0',(a(2) and b(0)),'0',s1(1),c1(2)); Fand03: fulladder port map('0',(a(3) and b(0)),'0',s1(2),c1(3)); --Row 1 Fand10: fulladder port map(s1(0),(a(0) and b(1)),c1(0),pro(1),c2(0)); Fand11: fulladder port map(s1(1),(a(1) and b(1)),c1(1),s2(0),c2(1)); Fand12: fulladder port map(s1(2),(a(2) and b(1)),c1(2),s2(1),c2(2)); Fand13: fulladder port map('0',(a(3) and b(1)),c1(3),s2(2),c2(3)); --Row 2 Fand20: fulladder ----Sin------A&B------Cin-Sout-Cout port map(s2(0),(a(0) and b(2)),c2(0),pro(2),c3(0)); Fand21: fulladder ----Sin--A&B------Cin-Sout-Cout port map(s2(1),(a(1) and b(2)),c2(1),s3(0),c3(1)); Fand22: fulladder ----Sin--A&B------Cin-Sout-Cout port map(s2(2),(a(2) and b(2)),c2(2),s3(1),c3(2)); Fand23: fulladder ----Sin--A&B------Cin-Sout-Cout port map('0',(a(3) and b(2)),c2(3),s3(2),c3(3)); --Row 3 Fand30: fulladder ----Sin------A&B------Cin-Sout-Cout port map(s3(0),(a(0) and b(3)),c3(0),pro(3),c4(0)); Fand31: fulladder ----Sin--A&B------Cin-Sout-Cout port map(s3(1),(a(1) and b(3)),c3(1),s4(0),c4(1)); Fand32: fulladder ----Sin--A&B------Cin-Sout-Cout port map(s3(2),(a(2) and b(3)),c3(2),s4(1),c4(2)); Fand33: fulladder ----Sin--A&B------Cin-Sout-Cout port map('0',(a(3) and b(3)),c3(3),s4(2),c4(3)); --Row 4 F40: fulladder port map(s4(0),c4(0),'0',pro(4),c5(0)); F41: fulladder port map(s4(1),c4(1),c5(0),pro(5),c5(1)); F42: fulladder port map(s4(2),c4(2),c5(1),pro(6),c5(2)); F43: fulladder port map('0',c4(3),c5(2),pro(7),c5(3)); end synth;
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3 answers

I'm rusty, but you may need to have explicit and shutters for the entries a(_) and b(_) . I heard about OR wires, but not about wires (at least in positive logic).

At the very least, try replacing each of them with just the a(_) and see if the errors go away. This will not be the correct scheme, but it will confirm whether I am correct about what causes the compilation problem.

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If I remember correctly, you cannot match a logical expression (for example, a (0) and b (0)) with a port (but I think the constants are ok). If this is correct, you must create explicit signals for all inputs and outputs.

also: 1) I don’t think the food-edder architecture is behavioral, so I would call it something else. I used (right or wrong) the rtl name for these architectures.

2) It is necessary to create an instance of full adders without declaring the component. Use type syntax

 Fand00: entity fulladder port map(...)

I also find it usual to always specify formal port names (cout => c1 (0), with some redundancy of the arrow direction, etc.)

3) I suppose you know that any recently new synthesizer will be able to synthesize multiplication and that you just do it to study how it works, otherwise I just told you :)

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Some synthesizers have problems with port cards that are not static expressions.

You may need to replace the expression on the port map with the signal where the synthesizer complains. For instance:

Fand00: fulladder port map('0',(a(0) and b(0)),'0',pro(0),c1(0));

WITH

signal t: std_logic;

...

t <= a(0) and b(0);

...

Fand00: fulladder port map('0',t,'0',pro(0),c1(0));

If at all possible, replace other synthesizer software. Do not torture yourself.

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