Geek Answers Handbook

How can I get a “complete” makefile if the makefile contains “include”?

Is it possible to get a “full” makefile if the makefile contains “include”? For instance:

#here is the contents of Makefile include inc1.i include inc2.i clean: rm -rf * #here is the contents of inc1.i abc: touch abc #here is the contents of inc2.i def: touch def

How can I get a “complete” makefile without including? Because when the Makefile includes another inc, and the inc file also includes another sub-inc ... it is very difficult to read!

I want to get a "full" make file, for example:

  abc: touch abc def: touch def clean: rm -rf *
+4
source share
4 answers

When using GNU make, I often found the output from make -p very useful (it will contain more than what you requested).

+3
source

To debug Make files using GNU Make, you can use

 make -p

to print (whole!) the make database, after you finish processing everything in your Makefiles. See GNU Make a Guide: Parameter Summary (this is the node information ("make) Parameter Summary").

This is probably a lot more information than you asked for - you may have to dig to find what you need.

Note that using the C preprocessor ("cc -E") will not work for the Makefile processing. Includes: C preprocessing processing processes the "#include", while the Makefile processing requires the processing of "include" and "-include" .

0
source

G'day

I find input make -np 2>&1 | tee results make -np 2>&1 | tee results to test the behavior of a makefile before doing make make is very useful. (Assuming bash, zsh, or something similar to trick stderr into stdout.)

NB Only the time when this does not work properly is that the makefile contains a command to create the local env code. expanding the tarball or creating a recursive copy of the source tree before entering and running the recursive make. For these cases, the analysis is performed in two stages, namely:

  • create a local copy as needed and comment out the command "cp -r" or "tar -xvf" applicable in the makefile, and
  • run make -np 2>&1 | tee results make -np 2>&1 | tee results , as before.

By the way. This was the only way to understand what was happening with the creation of an amazing project in which there were 20+ make files of about 2500 kSLOC code. There were also phases of code generation in the assembly to make life more interesting. (-:

NTN

0
source

You can do something like the following to get what you need.

 % cat include.mk define include-func dummy:=$(shell cat $(1) > /dev/stderr ) include $(1) dummy:=$(info include-func $(1) evaled, going to be included) endef dummy:=$(eval $(call include-func,include1.mk)) dummy:=$(eval $(call include-func,include2.mk)) all: include1-target include2-target #all done % cat include1.mk dummy:=$(info include1 being included) include1-target: @echo include1-target executed % cat include2.mk dummy:=$(info include2 being included) include2-target: @echo include2-target executed

actual conclusion:

 % make -f include.mk all dummy:=$(info include1 being included) include1-target: @echo include1-target executed include-func include1.mk evaled, going to be included include1 being included dummy:=$(info include2 being included) include2-target: @echo include2-target executed include-func include2.mk evaled, going to be included include2 being included include1-target executed include2-target executed #all done
0
source

More articles:


All Articles