VHDL How to add std_logic_vector along with std_logic signal?

Question

I have

douta : in std_logic_vector (3 downto 0); doutb : in std_logic_vector (3 downto 0); c0 : in std_logic; f1 : in std_logic; f0 : in std_logic; res : out std_logic_vector (3 downto 0); 

I am trying to create a simple ALU, and one of the functions that ALU provides is when

 f1 and f0 both = 1 res = douta plus b plus c0 

so i wrote

 f1 = '1' and f0 = '1' then res <= douta + doutb + c0; 

but it is obvious that it will not work, because the data type of douta and doutb is std_logic_vector , where as co is just std_logic

and I got this error while compiling

 ' Error 603 line 34 : Incompatible types for arithmetic operator: LHS=std_logic_vector!18, RHS=std_logic 

any idea how i can fix this problem?

also tried to change

 f1 = '1' and f0 = '1' then res <= douta + doutb + ("000" & c0); 

but still no luck, this time the compiler says

 LHS=std_logic_vector!7, RHS=array_1_of_std_logic_3_d_0 

Answer 1

Oh, I think I found a fix, I need to add the following library

 use ieee.std_logic_arith.all; 

and what we tried will work :) Thanks @jdehaan

Answer 2

Please do not use std_logic_vector if you are going to do arithmetic. Use ieee.numeric_std and use the signed or unsigned types. Then you can simply add your "0" or "1" to it.

The workaround for using std_logic_arith.all is fiction using a non-standard library, which can lead to portability problems when changing toolboxes.

I wrote a more detailed page about this: http://parallelpoints.com/node/3

This was discussed on comp.lang.vhdl here: http://groups.google.com/group/comp.lang.vhdl/browse_thread/thread/549e1bbffff35914d/83cc0f19350fc392?hl=en&q=group:comp.lang.vhdl+ numeric_std # 83cc0f19350fc392 , as well as in the frequently defined file comp.lang.vhdl.

Answer 3

You can convert c0 to std_logic_vector. I have been doing VHDL for a long time ...

 if f1 = '1' and f0 = '1' then if c0 = '1' then res <= douta + doutb + "0001"; else res <= douta + doutb; end if; end if; 

This is probably not so strong, perhaps the silicon compiler synthesizes it so well, maybe it is better to write it so that c0 is changed into a vector, and then all three douta, doutb and c0 converter are added. Another option is to make bit by bit bit by bit, but then why do you have a compiler?

This may sound ridiculous, but sometimes the compiler gives a better result if you give it some hints like this (just try and check the output with such a small example is not a big deal):

 if f1 = '1' and f0 = '1' then if c0 = '1' then res <= douta + doutb + "0001"; else res <= douta + doutb + "0000"; end if; end if; 

Another tip, if you write, if the results are somewhat strange, enter another to fix undefined states (some compilers behave badly if they have too much freedom!). But this is from my experience, which is already returning to the year 2004.

Answer 4

You do not need to convert std_logic to std_logic_vector to add. Just add as is and make sure that "res" has enough bits to hold the maximum response. In this case, res should be 5 bits wide so that it now overflows.

And as a nit style, don't call your input ports "dout". This is a bad form. Call them here because that is what they are. And in architecture, than when creating instances, you connect a different output port of the component named "dout" to the "din" of this component.