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Creating a VHDL Clone

I plan to develop a hardware modeling language such as VHDL for my project last year. How should I do it?

Any help would be greatly appreciated.

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If you want to create a hardware modeling language, start with the hardware.

Determine the level at which you want to simulate the device-transistor level, switch level, register level, behavior level and what is not displayed. From there everything else begins. Once this is resolved, you will learn which constructs your language should support.

You will need to know what devices your language can work with: transistors, gates, registers, multiplexers, memory, arithmetic units and what not. Then you need to find the appropriate model for each device.

In the end, you will definitely want to limit your area. Limit yourself to one. VHDL was not invented by one person in a day.

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Have you been given this project or the one you decided to do yourself? If this is the last, then you might want to rethink it, I'm afraid. Large open-end projects like this do not always end sadly for the student.

If you really want to do this, use VHDL yourself and read user comments on it. From this, you will learn what annoys or annoys your users, and then develops something better.

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If you are looking for more examples of parallel languages, there are MyHDL and XMOS XC, which are other attempts from traditional Verilog and VHDL.

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Developing a language is as simple as designing a specification. Do you plan to design a synthesizer and simulator to go with it?

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