Overriding the submenu of assigned variables in the parent makefile

Question

I use Make and I have a make file that sets a variable with a value that I need to override from the parent make file. I tried to set the variable in the parent makefile and use export to pass it to the submake, but the variable does not use the passed value, instead it uses the value explicitly set in the sub-Makefile.

I know that the variables specified on the command line override any normal assignments in the makefile (if override is not used), but is there any way to achieve this for the tabs without specifying it on the command line for each call (because there are many, and I like to stay dry)?

UPDATE

I should have mentioned that I cannot change the swap file because it is from the external repository that we are tracking, and I do not have the authority to change it, so I need to work at the parent makefile level to influence the fake.

Example

Here is a representative target in the parent makefile that causes the fake:

 $.PHONY (external_lib) $(external_lib): $(MAKE) -C $(source_dir)/project/component $(PROJECTVARS) make_a $(MAKE) -C $(source_dir)/project/component $(PROJECTVARS) make_b $(MAKE) -C $(source_dir)/project/component $(PROJECTVARS) make_c $(MAKE) -C $(source_dir)/project/component $(PROJECTVARS) make_d $(MAKE) -C $(source_dir)/project/component $(PROJECTVARS) make_e $(MAKE) -C $(source_dir)/project/component $(PROJECTVARS) make_f $(MAKE) -C $(source_dir)/project/component $(PROJECTVARS) make_g $(MAKE) -C $(source_dir)/project/component $(PROJECTVARS) make_h $(MAKE) -C $(source_dir)/project/component $(PROJECTVARS) make_i $(MAKE) -C $(source_dir)/project/component $(PROJECTVARS) library 

Answer 1

(You seem to be using something other than GNUMake, which is the only thing I know, so take this with salt.)

First, you can make your Makefile tidier by making components separate targets:

 COMPONENTS = make_a make_b make_c make_d make_e make_f make_g make_h make_i \ library .PHONY: external_lib $(COMPONENTS) $(external_lib): $(COMPONENTS) $(COMPONENTS): @$(MAKE) -s -C $(source_dir)/project/component $(PROJECTVARS) $@ 

(If you are worried about a clash of names, there are easy ways to handle this.)

Now, if you want to override a variable called, say, VAR, you can do it all in one place:

 COMPONENTS = make_a make_b make_c make_d make_e make_f make_g make_h make_i \ library .PHONY: external_lib $(COMPONENTS) $(external_lib): $(COMPONENTS) $(COMPONENTS): @$(MAKE) -s -C $(source_dir)/project/component $(PROJECTVARS) VAR=$(VAR) $@ 

It is assumed that you want to override the same variable for all components, as I read the question. If you want to override another variable for some purposes, this is easy:

 COMPONENTS = make_a make_b make_c make_d make_e make_f make_g make_h make_i \ library .PHONY: external_lib $(COMPONENTS) $(external_lib): $(COMPONENTS) VARNAME = VAR $(COMPONENTS): @$(MAKE) -s -C $(source_dir)/project/component $(PROJECTVARS) \ $(VARNAME)=$($(VARNAME)) $@ make_c: VARNAME=OtherVar make_h: VARNAME=YetAnotherVar 

If you want to redefine variables somewhat for some purposes, this is a bit complicated ...

Answer 2

If you do not want your subfile to override the value specified by the parent element, recompile it using the VARIABLE ?= value syntax. This will only perform the assignment if the variable is not already defined. In your case, the variable will be defined in the parent make file, so the assignment will not be performed.

Update: If you cannot change the sub file, you do not have a large number of options. I would probably recommend setting a variable on the command line when calling a sub file. For clarity, wrap these definitions in a make variable. For instance,

 CUSTOM_DEFINITIONS := VAR1=value1 VAR2=value2 VAR3=value3 $(external_lib): $(MAKE) -C $(source_dir)/project/component $(PROJECTVARS) $(CUSTOM_DEFINITIONS) make_a $(MAKE) -C $(source_dir)/project/component $(PROJECTVARS) $(CUSTOM_DEFINITIONS) make_b $(MAKE) -C $(source_dir)/project/component $(PROJECTVARS) $(CUSTOM_DEFINITIONS) make_c 

This is not the most suitable solution, but it can be done from the parent make file.

Answer 3

Besides using Export, which is not always recommended, you can pass variables to create such files -

 **HOSTCC = gcc** CC= MIPS-GCC FLAGS = -O2 -Wall -DSELECT_PROBLEM M="CC=$(CC) $(FLAGS)" 

all

 cd ../rng ; $(MAKE) $(M) **HOSTCC=$(HOSTCC)** ; 

therefore, if your sub file has 2 files, each of them requires a different compilation toolchain, you can do what is shown above.

Answer 4

Section 5.7.2 make.info (gnu make that is):

 The special variable `MAKEFLAGS` is always exported. ... Variables are _not_ normally passed down if they were created by default by `make` (Implicit Rules) if you want to export specific variables to sub-`make`, use the `export` directive. export VARIABLE ... 

So my recommendation is to either use the MAKEFLAGS variable, or explicitly export variable you want to use.

Answer 5

You will need to check if the variable already has a value before assigning it to sub-make.

From the GNU Make manual ( http://www.gnu.org/software/make/manual/make.html ) Section 6.5:

If you want a variable to be set to a value only if it is not already set, you can use the shorthand operator ?=' instead of ='. The two settings for the `FOO 'variable are identical (see" Start Function "):

  FOO ?= bar 

and

  ifeq ($(origin FOO), undefined) FOO = bar endif