Verilog for the GDSII Compiler (open source)

Question

Perhaps this question is not for StackOverflow, but both compilers and Verilog (which can be considered as a programming language) are related to this project.

Where can I find an open source compiler (either downloadable and free from non-commercial use) from Verilog to GDSII or Netlist? There are many Verilog simulators (which compile it to native machine code or C), many Verilog-FPGA compilers, but I need a compiler capable of generating geometric transition structures from Verilog.

Netlist http://en.wikipedia.org/wiki/Netlist - connection of IC elements, such as a transistor, resistor, or even cells (?). It can be converted to GDSII, but if the compiler works in "Verilog-> Netlist", I also need a free converter "Netlist-> GDS2".

GDSII http://en.wikipedia.org/wiki/GDSII is a VLSI (IC) integrated circuit format that is acceptable for backgrounds for making ICs. It's almost impossible for one person to get their GDSII fabricated at Silicon, but I think it might be interesting to try out small examples.

This compiler can use "full user" (it will draw all all transistors) or "cell-based" (verilog is compiled into a geometric set of some library cells).

Of course, the required compiler may be a university project that cannot compile a large verilog project.

Thanks.

Answer 1

Usually steps:

Verilog → [Compiler] → Gateway Connection List → [Location and Route Tool] → GDSII

You will also need an open source socket library. Do a quick search on the Internet and a place and route tool may appear.

Answer 2

This may be the last open source computing stack to be conquered; we already have GNU / Linux, GCC, and possibly some open source processors. But not a complete stream of chip design. What you call is called Place & Route (P & R) in Electronic Design Industry (EDA) jargon. As far as I know, there is no competitive VLSI flow in the open source community, the investments needed to develop a complete solution by location and route are very large in millions of dollars, for example, commercial tools: Design Compiler, Encounter from Cadence, IC compiler from Synopsis among others. Some of the algorithms for P&R take place in the academy, you can find the code here and there, but not a complete solution.

You can find SPICE, a circuit simulator that foundries and CAD companies use to create their cell libraries http://en.wikipedia.org/wiki/SPICE

These are some links to open source academic libraries, http://www.vlsitechnology.org/ http://www.vtvt.ece.vt.edu/vlsidesign/cell.php But I'm not sure if they can be used to real production. But, of course, this applies to the first ingredients of the EDA tool flow.

Prof. Andrew Kahng of UCSD, is a researcher at VLSI in UCSD, he maintains a list of useful lists of software for VLSI, here: http://vlsicad.ucsd.edu/Resources/SoftwareLinks/index.html , but some of the EDA paths are broken. This list from Berkeley may also be useful: http://embedded.eecs.berkeley.edu/pubs/downloads/

If you or someone can find some kind of open source P&R, let me know. Hope this helps.

Answer 3

Check out the Fedora FEL project: http://spins.fedoraproject.org/fel/#portfolio

Actual compilig tools for cell design http://www-asim.lip6.fr/recherche/alliance/doc/design-flow/tools.html#boog (VHDL only)