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Superscalar and VLIW

I want to ask a few questions related to ILP.

  • A superscalar processor is a kind of mixture of a scalar and vector processor. Can I say that vector processor architectures follow superscalar?

  • Processing multiple instructions at the same time does not make superscalar architecture, as it also provides pipelined, multiprocessor, or multicore architectures. What does it mean?

  • I read: "The superscalar CPU architecture implements a parallelism form called the parallelism instruction level in a single processor," superscalar use of more than one processor? Can someone provide me an example where a superscalar is used?

  • VLIW , I looked at this article, there is the number 4 on page 9. It shows the general implementation of VLIW, without a complicated reordering buffer and decoding and logic dispatching. The term without decoding confuses me.

Regards, anas anjaria

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4 answers

Check this article .

The main differences can be seen in these pictures:

Simple processor:

enter image description here

Superscalar processor:

enter image description here

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A superscalar processor is a kind of mixture of a scalar and vector processor.

LOL, no. A superscalar core is a core that can execute more than one command per cycle.

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A superscalar processor is a kind of mixture of a scalar and vector processor.

No, this is definitely not the case.

  • The scalar processor performs calculations on a piece of data at a time.
  • A superscalar can execute multiple scalar commands at a time.
  • VLIW can perform several operations at a time.
  • A vector processor can work with a data vector at a time.

The Haswell CPU superscalar that I type on this has 8 execution ports: 4 whole operations, 2 reads in memory and 2 stores. Potentially, 8 x86 commands can be executed simultaneously. This is a superscalar. The 8080 can only execute one command at a time. This scalar.

Haswell, both conveyor and superscalar. It is also speculative and out of order. It has hyperthreads (2 threads per core) and multi-core (2-18 cores). This is just a beast.

The parallelism command level (ILP) is a characteristic or measure of a program, not a CPU. The compiler scheduler will look for ILP statically or the CPU scheduler will dynamically search for ILP. If they find it, then they can order + follow the instructions accordingly.

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  • Check this out first ( http://en.wikipedia.org/wiki/Superscalar ):

    A superscalar processor executes more than one instruction during a clock cycle, while sending multiple instructions to redundant function blocks on the processor. Each function block is not a separate CPU core, but a runtime resource in a single processor, such as an arithmetic logic block, a bit shift, or a multiplier.

This means that, for example, a CPU with 2 (two) ALUs (arithmetic logic units) can physically issue 2 arithmetic instructions and execute them. Each arithmetic instruction will be executed in a different ALU.

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