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GNU make: variable for command line arguments

How to pass the entire command line (including targets, link lines, make parameters, etc.) from the top level to the recursive make:

targets : prerequisites $(MAKE) $(this should expand to top level command line) additional_args

Thanks.

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2 answers

I think that the closest you can use the combination $(MAKE) , which contains the exact file filename make, was called using $(MAKECMDGOALS) , which contains the goals you specify on the command line, and $(MAKEFLAGS) , which contains any definitions of variables and (a subset) of switches specified on the command line.

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The $(MAKE) macro is special and extends to include some relevant parameters. For more information, see How the MAKE Variable Works in the Make Documentation. However, this does not include the full line, including goals, etc., and I'm not sure if this is possible.

I usually try to avoid using Make recursively, there is a good article about it: Recursive evaluation is considered harmful .

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