VHDL Object and Architecture

With Ada, I can separate my modular modules into specification and body using .ads and .adb files.

Is it possible to separate the object and the VHDL architecture? If so, is there a naming convention or recommended style for this? And can objects fit in a user library / package?

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Libraries

Everything compiles to the library. By default, this is called β€œwork,” but you can override this. I rarely have to use this, although it is sometimes useful with an external IP address if there are namespace conflicts. As Chiggs noted, using libraries to create namespaces is good practice. Most synthesizers can now process multiple libraries , although this is not always the case. All simulators can (as far as I know). There's also a bit more hassle associated with setting them up (you have to tell the compiler where all of them are).


maybe an example - let's say you have an i2c controller and a spi controller. You can call both controller blocks and compile them into your own libraries called i2c and spi , and then create them as follows:

 i2c_instance:entity i2c.controller...etc spi_instance:entity spi.controller...etc 

or you can name them i2c_controller and spi_controller and follow these steps:

 i2c_instance:entity work.i2c_controller...etc spi_instance:entity work.spi_controller...etc 

And libraries are not "the same" as folders on the hard drive. They are managed by the VHDL compiler, so you create and map them using any syntax the tool uses.

For example, with Modelsim, vlib creates a library at a specific location in the file system (so it looks like a folder at that point), and vmap tells the compiler how to match the use some_lib; specific file system bit.

Objects, architectures, packages

You can split your object and architecture (or even more than one architecture per entity) into several files or save them in one file. Saving architecture in a separate file means that when you recompile it, you will not recompile the entity , which means that you do not need to recompile everything that creates it.

Similarly to packages and package body - bodies in a separate file mean that you can simply recompile this part without recompiling everything else. Please note that package not intended for placing objects.

(Aside - Modelsim has a -just switch, which allows you to store everything in one file and simply compile selected bits of files, for example, only parts of architecture and / or body ).

Summary

  • Compile reusable kernels into your own library to protect your namespace
  • Compile everything else in the work library
  • Put useful constants, functions, procedures, type definitions in one or more packages.
  • The inclusion of entities and architectures in one or more files is a matter of style of taste and development more than anything else.
  • Putting packages and packages in one or more files depends on taste and design style more than anything else.
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Essence and architecture are separate units of design. They can be in one file or can be in separate files. File extensions remain the same: usually .vhd , but .vhdl also possible. There is no generally accepted naming convention for file names. (Actually, there are hundreds of conventions, so this is just as useful as not a convention at all). Everything works; as an example, you can use myEntity.vhd and myEntity_RTL.vhd .

You can compile objects and architectures that you write in your own library. You can use your company name as the library name.

Don't confuse libraries with packages , though! A package is a compilation unit that contains reusable ads. A library is a named set of compilation units.

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