What happened to my blue VHDL function?

Question

library IEEE; use IEEE.MATH_REAL.ALL; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.NUMERIC_STD.ALL; entity SineGen is Port (clock : in std_logic; dac_ab_vpp : in integer range 0 to 4095; dac_cd_vpp : in integer range 0 to 4095; sine_dac_ab : out std_logic_vector(11 downto 0); sine_dac_cd : out std_logic_vector(11 downto 0)); end SineGen; architecture Behavioral of SineGen is subtype slv is std_logic_vector(11 downto 0); begin process(clock) variable count : integer range 0 to 255 := 0; variable temp_dac_ab : integer range 0 to 4095 := 0; variable temp_dac_cd : integer range 0 to 4095 := 0; begin if rising_edge(clock) then 

I tried everything and it comes down to the fact that the next two lines make the output always zero , and I don’t understand why. It should have been a sinusoidal output. (count - 256 samples per period. n - number of bits.) Are the following values ​​in a valid format?

  -- A*sin (2PI/2^n * count) temp_dac_ab := dac_ab_vpp * integer(round(sin(real(count * integer(math_2_pi/real(256)))))); temp_dac_cd := dac_cd_vpp * integer(round(sin(real(count * integer(math_2_pi/real(256)))))); if count < 256 then count := count + 1; else count := 0; end if; sine_dac_ab <= conv_std_logic_vector(temp_dac_ab, slv'length); sine_dac_cd <= conv_std_logic_vector(temp_dac_cd, slv'length); end if; end process; end Behavioral; 

Answer 1

In addition to what was mentioned in @brianreavis, you do not want to convert the fraction math_2_pi/real(256) to an integer, since it is always equal to 0. So:

 temp_dac_ab := integer(round(dac_ab_vpp * sin(real(count) * math_2_pi/real(256)))); temp_dac_cd := integer(round(dac_cd_vpp * sin(real(count) * math_2_pi/real(256)))); 

Answer 2

I'm realllyyy rusty with my VHDL, but I think you want this:

 temp_dac_ab := integer(round(dac_ab_vpp * sin(real(count * integer(math_2_pi/real(256)))))); temp_dac_cd := integer(round(dac_cd_vpp * sin(real(count * integer(math_2_pi/real(256)))))); 

(You don't want to round / cast the float from sin until you propagate it with dac_ab_vpp / dac_cd_vpp )