Makefile macro

Question

I would like to do something of my own, like a shell macro, where you can say $(shell command) .

Unfortunately, I did not find anything on the Internet on how to do this.

Is it possible?

Answer 1

In GNU, you can do something like the following. Imagine that you want to generate .h and .cpp file names from a simple file name without the extension that should be added as the source of some rule. You can write:

 define h_and_cpp_sources $(1).h $(1).cpp endef 

This creates a Makefile macro that receives the first parameter as $(1) , the second as $(2) , etc. Then:

 target: $(call h_and_cpp_sources,file) ... 

This will build a rule:

 target: file.h file.cpp 

Answer 2

You should try using the call function .

This is not exactly what you want, but AFAIK is nothing more complicated than that.