Both Philip and Martin provided excellent answers to your question, but I want to emphasize an important aspect of what VHDL is. VHDL is a tool that serves two completely different purposes.
On the one hand, it is a behavioral modeling language for describing parallel systems. Your model is compiled into an executable file and runs on your computer. This is what we call a simulator. This allows you to test the model during various execution states and simplifies debugging your design before proceeding to the next step: Implementation.
VHDL is also used as a metalanguage to describe the hardware architecture known as RTL. This description is translated into a list of primitives supported by your architecture (synthesis), and then placed and routed to a physical device.
It is important to understand the difference between these two uses in order to make full use of the language. Happy coding!
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