There is no such damper in the Linux kernel, there is a page from the Linux kernel about the cache and tlb: https://www.kernel.org/doc/Documentation/cachetlb.txt "Cache and TLB Flushing Under Linux". David C. Miller
In the 80386DX (and 80486 and, possibly, the "Embedded Pentium" was 10,000 MHz or the Embedded Pentium MMX 200-233 MHz "in 1998):
- 1 - The book "MICROPROCESSORS: 8086/8088, 80186/80286, 80386/80486 AND THE PENT FAMILY", ISBN 9788120339422, 2010, p. 579
This was done through the TR6 TR7 test registers:
- 2 - The book "Microprocessors and microcontrollers" from Godse & Godse, 2008 ISBN 9788184312973 page SA3-PA19: "3.2.7.3 Control registers" "Currently, only two test registers are defined (TR6-TR7) ... These registers are used for checking the translation viewing buffer (TLB) of the paging device. "
- 3 "x86-Programmierung und-Betriebsarten (Teil 5). Die Testregister TR6 und TR7", deutsche register article: "Zur Prüfung des Translation-Lookaside-Buffers sind die zwei Testregister TR6 and TR7 vorhanden. Sie werden als Test-Command- Register (TR6) and Testdatenregister (TR7) bezeichnet. "
- 4 Intel "Intel® Processor Family Design Guide for Embedded Pentium® Processors", Part "26 Specific Registers and Model Functions" page 8 "26.2.1.2 TLB Test Registers"
TR6 is a command register, a linear address is written to it. It can be used to write to a TLB or to read a string from a TLB. TR7 is data that must be written to or read from a TLB.
Wikipedia says in https://en.wikipedia.org/wiki/Test_register that reading TR6 / TR7 "generates an invalid operation code exception on any processor above 80486".
Mov tr6 / tr7 encoding is available only for privilege level 0: http://www.fermimn.gov.it/linux/quarta/x86/movrs.htm
0F 24 /r movl tr6/tr7,r32 12 Move (test register) to (register) movl %tr6,%ebx movl %tr7,%ebx 0F 26 /r movl r32,tr6/tr7 12 Move (register) to (test register) movl %ebx,%tr6 movl %ebx,%tr7
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