When are signals transmitted in VHDL?

Question

Given this code:

architecture synth of my_entity is signal a : std_logic; begin a <= c and d; b <= a and c; end synth; 

Will the second line respect that a changed in another process or all signals only at the end of the assigned architecture?

Answer 1

Caution with your terminology. When you say that a changed in another "process", it has special meaning in VHDL (a process is a keyword in VHDL), and your code has no processes.

Synthesizers will process your code as:

 a <= c and d; b <= (c and d) and c; 

Simulators usually assign a to the first pass, and then assign b to the second pass "delta" later. A delta is an infinitesimal time delay that takes place at the same time as the simulation, as the original destination.

Please note that this is a rough generalization of what is actually happening ... if you want complete information, read the documentation that came with your toolchain.

Answer 2

Will the second line respect what is changed in another process or all signals only at the end of the assigned architecture?

It looks like you are thinking about the behavior of a signal in a single process when you talk about it. In this context, signals are not updated until the end of the process, so update b will use the "old" value a

However, signal assignments not inside the process statement are performed continuously; there is nothing to “run” the architecture to “run”. Or, alternatively, they are all separate, separate implied processes (as you commented), with a list of sensibilities implied by everyone on the "right side".

In your particular case, assignment b will use the new value of a , and assignment will occur one delta cycle after assignment a .

For a readable description of how simulation time works in VHDL, see Jan Decaluwe's page here:

http://www.sigasi.com/content/vhdls-crown-jewel

And also this stream can be instructive:

https://groups.google.com/group/comp.lang.vhdl/browse_thread/thread/e47295730b0c3de4/d5bd4532349aadf0?hl=en&ie=UTF-8&q=vhdl+concurrent+assignment#d5bd4532349aadf0