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Why is MIPS Architecture divided into 4 areas?

The MIPS architecture software space has kuseg, kseg0, kseg1, and kseg2 memory segments. Is there a historical and logical reason for this separation?

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There are logical reasons for the existence of memory segments:

  • Caches in MIPS must be initialized with boot code (unlike x86 caches that are initialized by hardware).
  • The memory management module (MMU) in embedded systems is optional, therefore it is useful to have explicit areas of physical memory reserved for the kernel and not accessible by user mode code.

Here's what regions are used for:

  • KSEG1 addresses are not available and are not transmitted by MMU. KSEG1 is the only memory area that can be used in reset, because MMUs and caches on MIPS processors must be configured with a boot code that must be placed in KSEG1.

  • KSEG0 provides an address area for the kernel that is cached but not displayed by the MMU.

  • KSEG2 is used for kernel mode code, which is displayed by the MMU and cached.

  • KUSEG is used for user mode code that is displayed by the MMU and cached.

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