BRAM_INIT in VHDL

Question

I simulate a processor construct where the contents of the program memory are stored in BRAM. I am implementing program memory using VHDL (BRAM output). I try to avoid CoreGen because I want to keep the design portable. In the end, this project will move to FPGA.

I want to see if there is a way to initialize the contents of BRAM memory using VHDL generators? I understand that Coregen uses the COE file to initialize BRAM, but do we have VHDL-based code for this?

Let me know your alternative suggestions.

Answer 1

Yes it is possible. Take a look at the Xininx Synthesis Tool (XST) User Guide , in particular on page 187.

The code they recommend doing is reproduced below. The user guide has notes regarding the formatting of the file to be read. Please note that this code does not directly use generics, but I could assume that you could set a constant or a generic file name type ...

-- -- Initializing Block RAM from external data file -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use std.textio.all; entity rams_20c is port(clk : in std_logic; we : in std_logic; addr : in std_logic_vector(5 downto 0); din : in std_logic_vector(31 downto 0); dout : out std_logic_vector(31 downto 0)); end rams_20c; architecture syn of rams_20c is type RamType is array(0 to 63) of bit_vector(31 downto 0); impure function InitRamFromFile (RamFileName : in string) return RamType is FILE RamFile : text is in RamFileName; variable RamFileLine : line; variable RAM : RamType; begin for I in RamType'range loop readline (RamFile, RamFileLine); read (RamFileLine, RAM(I)); end loop; return RAM; end function; signal RAM : RamType := InitRamFromFile("rams_20c.data"); begin process (clk) begin if clk'event and clk = '1' then if we = '1' then RAM(conv_integer(addr)) <= to_bitvector(din); end if; dout <= to_stdlogicvector(RAM(conv_integer(addr))); end if; end process; end syn; 

Answer 2

Alternatively, do not use generators or read files; just declare a constant array in the package. Put it in a package, not in the main architecture, and you can even write the package automatically using a script (say reading the output of an assembler or a text file).

 library ieee; use ieee.std_logic_1164.all; package ProgMem is type Word is std_logic_vector(7 downto 0); constant ROM : array (0 to 3) of Word := ( X"C3", X"00", X"00", "UUUUUUUU" ); end package Progmem; 

The actual program may be longer, but this illustrates the pattern.