8259a PIC expects an INTA signal from the CPU. The CPU sends it when interrupt processing starts by passing the control to the corresponding ISR. Which ISR? The PIC passes a CPU interrupt vector that scans the IVT / IDT for the address, and you know everything else. The PIC will not feed the interrupt vector until it receives an INTA.
The 8259a PIC only has unidirectional communication with I / O devices. They may say that they have an interrupt that requires maintenance.
So, everything is in the air in the PIC if the processor does not respond to interruptions. However, devices can optionally cancel and then re-acknowledge interrupt request signals. I do not know what to do. I also don't know which ones take time to service interrupts.
If you are not interested in interrupts from a specific source, you can simply disguise it and you will not receive it. If you take an interrupt but don’t know how to handle it, you can simply tell the PIC that you processed it. This can lead to the fact that the interrupted device will be in a "frozen" state, waiting for an endless wait for service. It can also cause the device to maintain a high interrupt request signal, which will be a problem if you accept interrupts in the activated level mode - you will constantly receive interrupts.
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