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Conditional in a makefile that overrides a variable?

I have a variable in my makefile, I would like to either unset or override it, so that targets a , b and c use the correct MY_VARIABLE value (or nothing at all) inside their respective makefiles.

If I run make foo with the following:

 export MY_VARIABLE := 'false' foo: prep_foo dist prep_foo: $(shell export MY_VARIABLE='true') echo ${MY_VARIABLE} dist: abc a: make -C a/src b: make -C b/src c: make -C c/src

I get this output:

 export MY_VARIABLE='true' echo 'false' false ...

If instead I run make foo with the following make file:

 export MY_VARIABLE := 'false' foo: prep_foo dist prep_foo: $(shell unset MY_VARIABLE) echo ${MY_VARIABLE} dist: abc a: make -C a/src b: make -C b/src c: make -C c/src

I get the following output:

 make: unset: No such file or directory echo 'false' false ...

How can I cancel or override MY_VARIABLE when specifying a target (e.g. foo ) in this case?

EDIT

Here is a situation that I would like to avoid:

 dist: abc foo: a_foo b_foo c_foo a: make -C a/src ... a_foo make -C a_foo/src

I just want target a use a different value for my specific variable, so compilation is handled differently in this target makefile.

In addition, it does not look like export or unset variables in the target. For instance:

 dist: abc foo: a_foo b_foo c_foo a: make -C a/src ... a_foo: export MY_VARIABLE='true'; make -C a/src

If I try to do this, I get something similar to the following error in the line export MY_VARIABLE='true' (and similarly if I try to use unset ):

 Makefile:16: *** unterminated variable reference. Stop.

Does this help clarify what I'm trying to do?

EDIT 2

I tried a target in which the touch file is trying to run a child makefile target (which checks for the existence of the file):

 foo: prep_foo prep_foo: touch a/src/.foo make -C a/src

When I try to run this through make foo , I get the following error:

 Makefile:14: *** commands commence before first target. Stop.

If I remove the make statement from prep_foo , then I can touch file without receiving an error message, but I cannot start creating a , so this does not seem to help.

The following is the commands commence before first target error message:

 foo: prep_foo a prep_foo: touch a/src/.foo

Is there an example of using touch to pass state to child targets?

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2 answers

A common way to communicate between goals in a Makefile is through files. Just touch file for one purpose and check it in another. Could this help you solve your problem?

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Remember that every shell execution in make is executed in a new process. Trying to tinker with the environment variables of such recipes does not really make much sense - the environment that you modified on any given line disappears after this shell dies before the next line is executed.

You can do this work as follows:

 a: unset MY_VARIABLE; $MAKE -C a/src

or

 a: $MAKE MY_VARIABLE=foo -C a/src
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