I believe that you can use the value of the environment variable inside the make file.
Since I am new to bash and doing, it was a difficult time to figure out how.
I tried the following but did not succeed.
In bash
TEST_VAR=1 export TEST_VAR
In the make file
ifeq ($(TEST_VAR),1) COMMON_OBJECTS += Test1.o endif
But it does not compile Test1.cpp.
My makefile contains only these lines, and I add COMMON_OBJECTS to another variable defined in another file.
If I comment on this ifeq condition, then Test1 will be compiled. But I'm looking for a way to do this conditionally.
What am I missing here?
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