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What is the proper standard for makefiles?

I am currently writing small simple programs in C. At the moment, my Makefiles are composed of text something like:

program_name: clang -o program_name program_name.c

It's all I need? I was not sure whether to establish dependencies between the .o and .h files, even if they do not necessarily exist in my project.

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You work too hard. You should simplify the Makefile to 2 lines:

 CC=clang program_name: some.h

There is no need to specify a dependency on program_name.o or program_name.c , as they are implied. Also, you do not need to explicitly specify the rule, since you are using the default rule. However, dependencies on header files must be spelled out.

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I am using GNU Make yourself. Not sure what you are using. For GNU Make, refer to:

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It's all I need?

No.

I was not sure whether to establish dependencies between the .o and .h files

As a rule, you should, especially if you use custom data types (and even if not: changing the signature of the function can violate the entire program if the ABI / call conventions on your platform consist of black magic).

The template I use is usually:

 CC = gcc LD = $(CC) CFLAGS = -c -Wall LDFLAGS = -lwhatever -lfoo -lbar TARGET = myprog OBJECTS = $(patsubst %.c, %.o, $(wildcard *.c)) all: $(TARGET) $(TARGET): $(OBJECTS) $(LD) $(LDFLAGS) -o $@ $^ %.c: %.h %.o: %.c $(CC) $(CFLAGS) -o $@ $^
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